1. Field of the Invention
The present invention relates to a memory circuit, and, more particularly, to a multi-input memory circuit which has plural sets of clock signals and data signals and selectively uses an arbitrary set of clock and data signals to hold and output data.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing an example of a conventional memory circuit of the above type. This circuit has two systems of inputs (a data signal IN1 and clock signal CLK1, and a data signal IN2 and clock signal CLK2), and fixes the clock signal of a non-selected system to a logic value 1 so as to hold and output data of the selected system in synchronism with the rising edge of the clock signal of the selected system. This circuit mainly comprises an input circuit 4 and a latch 5 which is triggered at the rising edge of a clock signal.
To begin with, the one-input latch 5 will be described. This latch 5 has a first input gate 22, which receives a signal from the input circuit 4 and is enabled or disabled by an inverted signal CLKB of a clock signal CLK, a first hold circuit 12, which receives a signal from this first input gate 22, a second input gate 52, which is enabled or disabled by the clock signal CLK, a second hold circuit 42, which receives a signal from the input circuit 4 or the first hold circuit 12 via the second input gate 52, and an output circuit 1. The one-input latch 5 designed as above holds and outputs data in synchronism with the rising edge of the clock signal.
The first hold circuit 12 receives the output signal of the input circuit 4 from the first input gate 22, which is controlled by the inverted signal CLKB of the clock signal CLK, and holds the inverted signal of that input signal by means of a first feedback loop, which comprises a first inverting gate 2 and a first feedback gate 32. The second hold circuit 42 receives the output of the first hold circuit 12 from the second input gate 52, which is controlled by the clock signal CLK, and holds the inverted signal of that input signal or the value of the output signal from the input circuit 4 by means of a second feedback loop, which comprises a second inverting gate 3 and a second feedback gate 62.
The output circuit 1, which has an inverter 1A and an inverter 1B, drives a load (not shown) at the subsequent stage and guarantees the function of the second feedback loop. The first inverting gate 2 and second inverting gate 3 have a structure of an inverter, and the first feedback gate 32 and second feedback gate 62 have a structure of a clocked inverter.
The first input gate 22 and second input gate 52 both have a structure of a clocked inverter, and the first input gate 22 is enabled and the second input gate 52 is disabled during a period in which the clock signal CLK has a logic value 0. Accordingly, while the first feedback loop (first hold circuit 12) is holding the data signal, the second feedback loop (second hold circuit 42) keeps holding and outputting data of the previous cycle. While the clock signal CLK has a logic value 1, the first input gate 22 is disabled and the second input gate 52 is enabled. Accordingly, the data signal is cut off from the memory circuit and at the same time the data held in the first feedback loop (first hold circuit 12) is sent to the second feedback loop (second hold circuit 42). The second feedback loop (second hold circuit 42) holds and outputs this received data.
Through the above operation, when the clock signal CLK changes its logic value to "1" from "0", the data signal before the transition can be kept being output for one cycle after the transition. The "clocked inverter" is a logic gate, which functions as an inverter only when the control signal has a logic value 1 and whose output has a high resistance when the control signal has a logic value 0.
The input circuit 4 will now be described. This input circuit 4 selects one system of data from two systems of data, and outputs it to the above-described one-input latch 5. The two systems of clock signals CLK1 and CLK2 input to this input circuit 4 are input to an AND gate, which comprises a NAND gate 301 and an inverter 302, to be converted into one system of a clock signal. The data signals IN1 and IN2 are input to a select gate, which comprises three NOR gates 303, 304 and 305, to be converted into one system of a data signal.
This select gate has a structure of a multiplexer, which becomes active when the control signal has a logic value 0. For example, to use one set of the clock signal CLK1 and data signal IN1, the clock signal CLK2 is fixed to a logic value 1. In this case, the AND gate comprising the NAND gate 301 and inverter 302 always outputs the clock signal CLK1. As the clock signal CLK2 always has a logic value 1, the NOR gate 304 always outputs a logic value 0, causing the NOR gate 305 to always output the output of the NOR gate 304. That is, the clock signal CLK becomes the clock signal CLK1, and the output of the NOR gate 305 becomes the data signal IN1. Through the above operation, a memory circuit with multi-input signals can be accomplished.
As the scale of semiconductor integrated circuits become larger and their designs become complex today, it becomes difficult to provide a detailed evaluation of the internal structure of an integrated circuit. The number of integrated circuits in which a self-evaluating device is incorporated is increasing. Of those circuits, a so-called scan bus system is employed in many semiconductor integrated circuits due to its relatively simple structure and its easy evaluation method.
The scan bus system is a method of evaluating the internal structure of an integrated circuit by connecting latches or registers to be evaluated in a row and outputting their contents as serial data. According to this method, while the individual latches hold and output received data in synchronism with a clock signal from the system in normal operation mode, each of the latches connected in a row shifts its content to the next latch, thereby outputting their contents as serial data, in synchronism with a test clock signal in test mode. Accomplishing this function, therefore, requires a memory circuit which selectively uses the logic connection in normal operation mode or the connection of the latches for the test mode.
There are several possible ways to select the normal operation or an operation in test mode. What relates to this invention is a memory circuit which is suitable particularly for the case where the normal operation or the test-mode operation is selected by the simplest system of disabling a test clock signal in normal operation mode and disabling a clock signal for the normal operation in test mode.
Since the above-described conventional multi-input memory circuit requires a signal coming through a logic gate as a clock signal and uses a separate system of circuit to select data, however, it has the following shortcomings.
First, the clock signal lags by a delay caused by traveling through the NAND gate 301 and inverter 302, so that the delay of the clock signal is wasted every cycle, as compared with an ordinary memory circuit of a single-system type.
Secondly, since the data signal and clock signal pass separate logics, it is difficult to design the timings for the setup and hold.
Particularly, the skew and delay of the clock signal is always the bottleneck on the design in recent high-speed semiconductor integrated circuits, and the driver and the traveling path for the clock signal are designed very prudently. Therefore, the circuit configuration which causes the clock signal to pass through a gate and the circuit configuration which disturbs the regularity of that timing, as of the above-described conventional memory circuit, disadvantageously increase a burden on the circuit design.